This invention relates generally to processes for manufacturing semiconductor integrated circuits.
Copper seed layers are generally deposited on Cu diffusion barrier materials to enable those materials to receive copper electroplating. However, as silicon processes move to ever smaller features, the ability to deposit copper seed layers, for example using physical vapor deposition techniques, with minimal overhang and asymmetry, adequate sidewall coverage and a sufficient field thickness for gap fill is increasingly in doubt.
Physical vapor deposition of barrier materials has associated overhang, asymmetry, and sidewall coverage issues prior to copper electroplating. Physical vapor deposition of copper seed layers may further reduce the plating budget within a given feature. Alternatively, a wafer may be immersed in a palladium solution to chemically activate the surface prior to electroless plating of a copper or a copper diffusion barrier. However, this involves an additional chemical expense, process step and bath recycle requirements prior to electroless barrier deposition.
In general there is a need for better ways to form materials on dielectric materials.